04. Modifying the MIPS Chip

$\gdef \N{\mathbb{N}} \gdef \Z{\mathbb{Z}} \gdef \Q{\mathbb{Q}} \gdef \R{\mathbb{R}} \gdef \C{\mathbb{C}} \gdef \setcomp#1{\overline{#1}} \gdef \sseq{\subseteq} \gdef \pset#1{\mathcal{P}(#1)} \gdef \covariant{\operatorname{Cov}} \gdef \of{\circ} \gdef \p{^{\prime}} \gdef \pp{^{\prime\prime}} \gdef \ppp{^{\prime\prime\prime}} \gdef \pn#1{^{\prime\times{#1}}} $

The slides for this unit are short and rather confusing. The unit is about extending the MIPS chip to allow for additional commands, but the only thing in the slides are two examples, and very little elaboration. However, here’s what seemed important from the slides:

Things to consider when extending the chip:

1. What hardware will need to be added?
   • All hardware is allowed to be added, without explaining the inner mechanisms, but it’s functionality must be explained.
2. What will the values on the new control lines for that hardware be for each cycle when executing the new command? What changes will be made to existing control lines?
3. What will the component output at each cycle
4. What will the values on the new control lines be when executing preexisting commands?

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